`timescale 1ns/1ns

module s_to_p(
           input clk ,
           input rst_n	,
           input	valid_a	,
           input	data_a	,

           output	reg ready_a	,
           output	reg	valid_b	,
           output reg [5: 0] data_b
       );
reg [2: 0] cnt;
reg [5: 0] data;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			ready_a <= 0;
		else
			ready_a <= 1;
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			cnt <= 3'd0;
		else if (valid_a & ready_a)
			begin
				cnt <= (cnt == 3'd5) ? 3'd0 : (cnt + 1'b1);
			end
		else
			cnt <= cnt;
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			data <= 'd0;
		else if (valid_a & ready_a)
			data <= {data_a, data[5: 1]};
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				valid_b <= 0;
				data_b <= 6'd0;
			end
		else if (cnt == 3'd5 )
			begin
				valid_b <= 1;
				data_b <= {data_a, data[5: 1]};
			end
		else
			valid_b <= 'd0;
	end
endmodule
